1. Field of the Invention
The present invention relates generally to an asynchronous-to-synchronous interface between two chips. More particularly, the present invention relates to an asynchronous-to-synchronous interface between a microprocessor and a target chip where the transfer of data to the target chip from the microprocessor is in parallel.
2. Related Art
Many computer-based integrated circuit (IC) chips are interfaced to a master chip. Often, the target chip has a clock that is running at a different speed or phase than the clock of the master chip. When the master chip transfers data (e.g., address, control, data, etc.) to the target chip, the two chips must be synchronized in some fashion. This problem is called asynchronisity.
One conventional solution to the asynchronisity problem is to transfer data from the master chip to target registers (on the target chip) with a write pulse which is a function of the timing characteristics of the master chip (known as synchronous write architectures or interfaces). Such synchronized interfaces are small in area and require little power. They can also operate cleanly, because metastability is transferred from the data path to the control path. On the downside, synchronous write architectures require an active clock to write to registers on the target chip and typically the minimum guaranteed write-to-write time is two clock periods (one clock period due to asynchronism and one period accounting for internal writing on the target).
Another conventional solution to the asynchronisity problem is to employ an asynchronous write system architecture as an interface between the two chips. In such a system, no clock is required to write to registers on the target chip, but a clock is required to synchronously transfer (if desired or required) data from the target registers to the internal parts of the target chip.
An example of an asynchronous write system architecture is shown in FIG. 1, which is a block diagram illustrating a standard asynchronous-to-synchronous interface 100 employed on a target chip 102. The target chip 102 is coupled to a microprocessor chip (master, not shown). The microprocessor (sometimes referred to herein as the master chip or central processing unit) communicates with the target chip 102 by transferring data bits, control bits and address bits to the target chip 102. The data bits are typically some form of numeric or alphanumeric binary code that is processed in an implementation dependent manner by logic circuits (not shown) on the target chip 102. The control signal includes a clock signal (referred to as an asynchronous write signal, because the internal clock 118 of the target chip 102 and the internal clock, not shown, of the microprocessor operate at different speeds) generated by the microprocessor. This clock signal controls when the data bits are written into the target chip 102. The address bits specify a location in the target chip 102 where the data bits are to be written. The data bits are transferred in parallel via bus 112. The control signal is transferred via a bus 114 and the address bits are transferred via a bus 113, the data bus 112 is N bits wide. The address bus 113 is M bits wide, and the control bus 114 is C bits wide. N is often 8-bits, 2.sup.M is the address space, and C is often 3-bits (Chip Select, Write and Read). The data and address may also be time multiplexed on the same bus.
The target chip and the microprocessor chip operate at different speeds and/or unknown phasing. The microprocessor transfers data to the target chip 102 at a rate controlled by the microprocessor chip. The target chip 102 writes the data (transferred from the microprocessor) to logic circuits located on the target chip 102 with a timing controlled by the target chip 102 (specifically, at a timing determined by an internal clock 118 of the target chip 102).
To solve this asynchronisity problem, the target chip 102 employs a conventional interface shown as 100. The interface 100 includes: an internal clock 118, edge triggered latches 104A-N, 106A-N, and 108A-N, an address decoder 110 and AND gates 116A-N. N is equal to the width of the data bus 112, such that there is one latch 104A-N, for example, for every data bit transferred over the data bus 112. In this example, latches 104, 106 and 108 are edge triggered flip-flops.
The address decoder 110 is comprised of standard address decode circuitry (e.g., typically gates). Multiple address bits travel in parallel on bus 113 from the microprocessor (not shown) to the address decoder 110. The address decoder 110 responds by activating (that is, setting to a logical high value, or to a logical 1 value) one of its outputs 140A-N. Generally, one and only one of the output terminals 140A-N will be activated for each possible address. When a rising edge of the asynchronous write signal is transferred via bus 114 to the AND gates 116A-N, on the next trailing edge of the asynchronous write signal, this latch 104A-104N latches in the data bit present on the data bus 112. In this manner, data bits are asynchronously transferred from the microprocessor to the target chip 102 and, in particular, to the latches 104A-N of the target chip.
As will be appreciated, the latches 104 are not sufficient by themselves to latch in the data bits, because they are asynchronous to the target chip. To synchronously transfer the data in latches 104, another bank of latches, 106, accepts the asynchronous data presently in latches 104 at a clock edge from clock 118. This is still insufficient to guarantee robust synchronous transfer because of metastability.
Metastability is the condition where data on the bus 112 arrives at a latch 104 simultaneously with a rising edge of the asynchronous write signal. A single latch 104 would propagate possibly incorrect data if metastability occurs. The latches 104, 106, 108 in each data path alleviate metastability by preventing possibly incorrect data from being propagated to logic circuits (now shown) in the target chip. Specifically, each latch 104 is connected in series to a latch 106/latch 108 pair (equivalently, a latch 106/latch 108 pair is associated with each bit transferred over the data bus 112). Latches 106 and 108 are controlled by the internal clock 118 to enable the synchronous transfer of data from the latches 104 to other logic circuits in the target chip 102 (denoted as "To Target Chip Logic" in FIG. 1.)
Listed below are several undesirable aspects of the standard architecture interface 100 shown in FIG. 1. The problems are as follows: (1) Two latches 106A-N and 108A-N are required for each data bit which is to be synchronized (that is, each data bit transferred via the bus 112). Where the data bus 112 is 16-bits wide, 32 latches (flip-flops) 106, 108 are required. That is, the conventional interface 100 requires substantial "real estate" (i.e., chip area) on the chip 102. (2) The clock signal produced by clock 118 must drive two latches 106A-N, 108A-N per synchronized bit, in addition to other flip-flops on the chip 102. Consequently, substantial power is dissipated (power burn) by chip 102 from the need to drive so many flip-flops. Additionally, chip 102 also consumes excessive power due to capacitance caused by routing data between latches 106A-N, 108A-N. Such capacitance is often aggravated by the need to widen high speed internal clock runners for electromigration abatement. (3) Ambiguous data--For instance, it is possible for latches 106 and 108 to propagate incorrect data (e.g., not before or after data values for one clock cycle). Specifically, the data 112 propagated through 104 may be changing at the time the data is latched into latches 106 with some data values at their new values and some still at their old values. Neither the complete original data values nor the new data values are clocked into latches 106 and subsequently into latches 108 for one clock cycle. This problem is aggravated if latches 104 are implemented as level sense flip-flops due to routing delay differences in data bus 112; and still remains if latches 104 are implemented as edge-triggered flip-flops due to asymmetrical rise and fall times in latches 104. And (5) latches 106A-N, 108A-N do not completely solve the metastability problem.
Therefore, what is needed is an improved asynchronous-to-synchronous interface that does not suffer from the above-described problems associated with conventional interfaces.